Designs for testing and testability play an important role in the design and manufacture of integrated, circuits. State of the art multimedia applications involve very high speed data transmission and reception. Data channels in transmitter (TX) and receiver (RX) devices may need to be tested at operational speed in order to expose faults and errors in the physical layer (PHY) implementation of TX and RX circuits. At-speed testing of data channels usually requires clocks of speeds corresponding to bit speeds of the data channels. However, it is often impractical and power intensive to generate such high speed clocks in test mode.
For example, a High-Definition Multimedia Interface (HDMI) is popularly used in connecting digital video sources, such as, DVD players and personal computers, to digital display devices, such as, televisions and computer monitors. An HDMI component may accept multiple channels of data, such as, Red Green Blue (RGB) components of source video in compressed parallel format and transmit the data as uncompressed serial digital data streams to the digital display devices.
With reference to FIG. 1, there is shown a conventional HDMI TX PHY 100. Input ports 103a-c of serializer 110 accept RGB data channels 102a-c respectively, as shown. Each of the RGB data channels 102a-c are 10-bit wide buses, and clocked at a standard frequency of 148.5 MHz, using pixel clock 106, derived from Phase Locked Loop (PLL) 112. The data is serialized by serializer 110 and driven on output ports 105a-c as single bit RGB data buses 104a—c. Due to the serialization, each of the data buses, 104a-c, carry 10 bits of data in a single cycle of the pixel clock 106. In other words, the data buses 101a-c are driven at 10 times the bit rate of the pixel clock, 10×148.5 MHz, or 1.485 GHz.
Accordingly, in order to properly test the serialized data transmitted on data buses 104a-c, a 1.485 GHz bit clock needs to be generated. Generating and operating clocks at such high speeds incurs very high power consumption. Moreover, it is often unfeasible to generate such high frequency clocks using traditional clock generation methods, in test mode. As the speed and frequency demands on data transmission keep increasing, the problem is exacerbated. Accordingly, there is a need in the art for efficiently testing high speed data channels, such as, data buses 103a-c, while avoiding the aforementioned problems associated with high speed bit clocks.